Apparatus for driving a light emitting diode of horologic display

ABSTRACT

There is disclosed a logic and driving circuit for a light emitting diode type horologic display in which three diodes are read out at any given time to represent the time of day. Power consumption is kept to a minimum by the use of a two voltage level system with the lower voltage supplying those portions of the circuit working at a high frequency while the higher voltage supplies the display and those portions of the driving circuit operating at a considerably lower frequency. In addition to a crystal frequency standard and a &#39;&#39;&#39;&#39;divide-by-two&#39;&#39;&#39;&#39; flip-flop countdown circuit which provides a 1 Hz signal to a series of toggle flip-flop counting circuits which function as the seconds, minutes and hours storage elements, there is provided a multiplexer coupled to the outputs of these counting circuits which is strobed with pulses having a combined duration of only a fraction of the sampling cycle. This results in a low duty cycle for the output of the multiplexer and thus for the display itself which conserves on the power necessary to drive the display. Since hour, minute and second information is sequentially sampled by the multiplexing circuit, multiplexing eliminates decoder and driver redundancy. Provision is made in the multiplexing logic for dividing the horological display into quadrants or sectors so as to further reduce the number of driver and decoder elements. As a result there is also provided a quadrant selecting circuit. The sampling pulses for the multiplexing circuit are conveniently derived from the frequency standard countdown circuit. The driving system utilizes complementary metal oxide semiconductor (CMOS) components in which power drain is minimized because these elements draw appreciable power only when switching. A further power consumption advantage is obtained by utilizing NAND gate logic to permit the use of these low power CMOS components. Toggle flip-flops are chosen for the counters because they are available in metal oxide semiconductor form and because the total number of transistors utilized is reduced. The logic described herein is used with a horologic display in which the minutes and seconds are displayed in the single ring of elements with the hours being displayed in another single ring of elements.

United States Patent Daniels [111 3,754,392 1451 Aug. 28, 1973 3/1971Walton 58/23 X Primary Examiner-Richard B. Wilkinson AssistantExaminer-Edith C. Jackmon Attorney-Mueller and Aichele ABSTRACT There isdisclosed a logic and driving circuit for a light emitting diode typehorologic display in which three diodes are read out at any given timeto represent the time of day. Power consumption is kept to a minimum bythe use of a two voltage level system with the lower voltage supplyingthose portions of the circuit working at a high frequency while thehigher voltage supplies the display and those portions of the drivingcircuit opl.5 VOLT SUPPLY (HIGH FREQUENCY CIRCUITS) crating at aconsiderably lower frequency. In addition to a crystal frequencystandard and a "divide-by-two flip-flop countdown circuit which providesa 1 Hz signal to a series of toggle flip-flop counting circuits whichfunction as the seconds, minutes and hours storage elements, there isprovided a multiplexer coupled to the outputs of these counting circuitswhich is strobed with pulses having a combined duration of only afraction of the sampling cycle. This results in a low duty cycle for theoutput of the multiplexer and thus for the display itself whichconserves on the power necessary to drive the display. Since hour,minute and second information is sequentially sampled by themultiplexing circuit, multiplexing eliminates decoder and driverredundancy. Provision is made in the multiplexing logic for dividing thehorological display into quadrants or seetors so as to further reducethe number of driver and decoder elements. As a result there is alsoprovided a quadrant selecting circuit. The sampling pulses for themultiplexing circuit are conveniently derived from the frequencystandard countdown circuit. The driving systemutilizes complementarymetal oxide semiconductor (CMOS) components in which power drain isminimized because these elements draw appreciable power only whenswitching. A further power consumption advantage is obtained byutilizing NAND gate logic to permit theuse of these low power CMOScomponents. Toggle flip-flops are chosen for the counters because theyare available in metal oxide semiconductor form and because the totalnumber of transistors utilized is reduced. The logic described herein isused with a horologic display in which the minutes and seconds aredisplayed in the single ring of elements with the hours being displayedin another single ring of elements.

19 Claims, 13 Drawing Figures 1 i 1 I I 110 11s 1 n C I 1 F 4 F 1 i 1 I1 Hz ll I F/F F/F---F/F I I I 1 l 1 1 1 1 1 1 I16 116 11s I 1 1 El i 256111V lza Hz 1 l i l -64 Hz 1 i i 1 1 1 1 l 9- J L PPE BQ'Q 1 I l 1 l l 1160 1 n 1 i 130 12,1 132 TIME SET f g 1 sec MIN. HR, 1 COUNTER COUNTERCOUNTER DECODER 1 136 I z Y /?133 771a4 /?135 l I SEC. m,"- 1

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FROM DRIVER Patented Aug. 28, 1973 3,754,392

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Patented Aug. 28, 1973 1 1 SheetsSheet 7 lI orA I Or I! =5 w M m M a M AN k M v MINJSECJHR. MULTIPLEXERJI Illlulllllllllll INVENTOR. R. GaryDanie/s WM M Arrrst Patented Aug 28, 1973 1 1 Sheets-Sheet 8 ISO DECODERI I l i l l l I l Arrrs.

Patented Aug. 28, 1973' 11 Sheets-Sheet 9 Arrris.

Patented Aug. 28,1973 I 3,754,392

11 Sheets-Sheet ll 7 SEC.

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- MIN.

I E E 5* J INVENTOR BY 1?. Gary Danie/s i 2/ 2 4 ATTYS APPARATUS FORDRIVING A LIGHT EMITTING DIODE OF I-IOROLOGIC DISPLAY BACKGROUND OF THEINVENTION This invention relates to horologic displays and moreparticularly to a system for providing a digital readout for a horologicdisplay in which the minutes and seconds are displayed in a first ringof elements with the hours being displayed in a second ring of elements.

There has in the past been a great deal of interest shown in theprovision of a digital readout for wrist watches. Wrist watchesutilizing digital readouts have recently been provided with readouts inalpha-numeric form utilizing an XY addressable matrix of individuallight emitting diodes. The circuits necessary for driving XY addressablelight emitting diode arrays are well known. However, alpha-numeric lightemitting diode displays suffer from one major problem when they areutilized to portray the time of day in a wrist watch. This problem isprimarily power consumption. Power consumption is so great in wristwatches utilizing alphanumeric displays that the battery for the wristwatch mustbe replaced within a matter of weeks if the'display is to runcontinuously. The reason for the amount .of power drawn by alpha-numericdisplay type wrist watches is the number of :light emitting elementsnecessary toportray the time of day. In an effort to increasethelifetime of the wrist watch there is provision for intermittentreadout which is-activated by the user of the wrist watch. This is bothinconvenient and annoying to the user.

Thesubject system is employed in a time readout of adifi'erent characteraltogether. The time of day is read out by a maximum of three lightemittingdiodes. In one configuration, 60 light emitting diodes arearranged in a ring and represent both minutes and seconds. An innerconcentric ring of 12 light emitting diodes represents the 'hour of day.The time is read out in this display by providing that the hour diode besubstantially continuously lit for the "hour it represents. In the outerring the minute diode remains litsubstantially continuously for theminute that it represents. While :the minute diode is lit the remainingdiodes in the outer ring are lit sequentially so as to representseconds. Thus,for any given minute-all 60 diodes representing secondsare lit sequentially in a clockwise stepping type .display. After theseconds have stepped around a full 60 seconds, the next minute diode isactivated. it will be appreciatd that in this type display the 60 diodesin the outer ring serve both to represent minutes and seconds. It willbe further appreciated thatthe time of day can be read out with amaximum of 3 diodes during any given second. This compares to a maximumof 87 diodes to represent the time of day in alpha-numeric form.

The subject system isone which providesthelogic and driving circuitsnecessary to actuate the above mentioned light emitting diodes in theproper sequence. In the concentric ring display, it is possible toreduce the current drawn by such a display to 5 milliamps or less byreducing what is known as the duty cycle-of the display. This refers .tothe'practice of lighting each light emitting diode, not continuously,but in alpulsed manner'such that the diode is lit only for a certainpercentage of time. The logic portion of the circuit to be describedherein in combination with the driving portion not only actuates thedisplay in proper sequence, but also provides the low duty cycle. Thelogic and driver portions utilize only an insignificant additionalamount of current therefore enabling a light emitting diode horologicdisplay which can be read out in a substantially continuous manner for aperiod of time exceeding one year without the necessity of providing forintermittent readouts to extend battery lifetime.

Power consumption in the logic and driving circuits are kept to aminimum by the use of several individual concepts. The first of theseconcepts involves the use of two voltage levels in the operation of thedisplay. For those circuits having a high frequency of operation (i.e.,almost continuous operation), a lower voltage such as 1.5 volts is usedto minimize power consumption. These type of circuits are the crystaloscillator circuit and the countdown circuit which are utilized inreducing the frequency of the crystal oscillator to l .Hz. The remainderof the circuit, that is to say the minute, second and hour countingcircuits, the multiplexer circuits, the decoding circuits, and thedriving circuits, as well as the light emitting diodes themselves, are,provided with a 3 volt supply. It will be appreciated that these lattercircuits are operated at a considerably lower frequency than thecountdown circuitry. Although the higher voltage is desirable in orderto drive the light emitting diode elements, power is conserved becauseboth the duty cycle of the light emitting diode :elements and the dutycycle of the drive circuitry isreduced to as low as 12.5 percent totalon time perelement. Thus, while it is necessary to increase the voltageto these circuits in order to provide driving power for the lightemitting display, this power is utilized over a low duty cycle whichcorresponds to alower frequency of operation.

Another power saving portion of the invention involves the useofcomplementary metaloxide semiconductors (CMOS) as switching elements andin the counters. It will be appreciated that the metal oxidesemiconductor devices draw current only when they are switching (i.e.,changing state).

In addition to power consumption advantages'of the subject circuit, themultiplexing circuit utilized herein eliminates redundancy in thedecoder and driver elements necessary for driving the hours, minutesandseconds portions of the display. The numbers of elements are alsodecreased by provision of .a quadrant or sector system of addressing thelight emitting diode elements. An additional and a most importantfunction of the multiplexing circuit is to reduce the aforementionedduty cycle. What the multiplexing circuit does is to sample the seconds,minutes, and "hour counters at a high repetition rate with a low dutycycle as dictated'by sampling pulses of short duration. If theinformation in the counters is sampled once every onesixty-fourth of asecond, the information is actually flowing out of the multiplexer foronly a small portion of this one sixtyfourth second time period clue tothe short sampling pulses. At all othertimes, the output of themultiplexer is inhibited. Thus'the multiplexer II'I'BddIIIOII tosequentially reading out the information stored in the counters alsoserves the purpose of reducing-the duty cycle ultimately for the lightemitting diode in the display. A further advantage occurs with themultiplexing circuit when used in conjunction with a display in .whichtime is displayed by three diodes. Although it looks as if three diodesare continuously lit during one sampling cycle, this is not so. In anygiven sampling period only one diode is lit at a time. This is becausethe seconds, minutes and hours information is not simultaneously readout but rather is read out over mutually exclusive time intervals. Thismeans that peak battery current drain is minimized so that highimpedance batteries may be used.

The sampling is accomplished in the subject circuit by coincident gatingwithin the multiplexer circuit. The timing pulses for the sampling arederived from the aforementioned divide-by-two countdown circuit whichprovides the I Hz signal for driving the counters.

In addition, the counters consist of toggle-type flipflops which are soarranged to have a binary output. These toggle-type flip-flops areutilized rather than JK- type flip-flops because of the aforementioneddecrease in number of transistors necessary. While toggle-typeflip-flops are usually utilized only in countdown circuits, they areutilized in this application as binary encoders. In the configurationsto be described herein the toggle-type counters are easily matched to aNAND- type decoder circuit which is also available in MOS form.

It will be appreciated that the choice of the two level voltage in astrobed multiplexer circuit, MOS type components and the logic to bedescribed are important primarily because of power consumption savings.They are further chosen because of the saving of individual componentparts. 11

SUMMARY OF THE INVENTION It is therefore an object of this invention toprovide an improved logic and driving system for use in light emittingdiode horologic display.

It is a further object of this invention to provide in combination anoscillator circuit; a divide-by-two countdown circuit for providing a IHz signal; seconds, minutes and hours counters cascaded to form storageelements having an output in binary form; a multiplexer circuit whichprovides for sequential readout of the seconds, minutes and hourscounters as well as providing for a low duty cycle driving signal; abinary-to-pulse decoder, and a driving circuit which responds to thepulsed output of the decoding circuit for actuating individual lightemitting diode elements in the horologic display.

It is a still further object of this invention to provide a horologicdisplay in which the time is represented by an outer ring of elementsrepresenting seconds and minutes, and an inner ring of elementsrepresenting hours in which the outer ring of elements is dividedintosectors such that all the elements are driven by a single driverconnected in parallel with the corresponding elements in each sector andis further provided with a sector selector such that only one sector andtherefore only one element in each sector is driven at any one giventime.

It is a still further object of this invention to provide a drivingcircuit for a light emitting diode horologic display in which the highfrequency circuits are powered by a first voltage while the lowerfrequency circuits are powered by a second voltage higher than the firstvoltage such that power consumption is minimized.

It is a still further object of this invention to provide a binary logicsystem utilizing toggle flip-flops and NAND gate reset logic to provideinformation which when decoded and supplied to a driving circuitactuates the light emitting diode display.

It is a still further object of this invention to provide a multiplexedlogic and driving circuit for light emitting diode display in which themultiplexing circuit samples seconds, minutes and hour informationavailable in binary form from counters in a sequence and for a samplingduration which minimizes the duty cycle of the light emitting diodes inthe display while at the same time conserving on the number of drivingelements, thereby conserving greatly on the power dissipated both by thedriving circuit and by the light emitting diode display elements.

It is yet another object of this invention to provide logic and drivecircuitry for a horologic display utilizing a logic permitting the useof metal oxide semiconductor logic parts.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing thelogic and driving circuits for a light emitting diode display;

FIG. 2 is a diagrammatic view indicating the manner in which the time ofday is read out from the aforementioned light emitting diode display,also indicating an asymmetrical sector arrangement indicating inaddition the method of actuation from the output of the driver shown inFIG. 1;

FIG. 3 is a block diagram showing generically the circuit configurationsof the multiplexer, the decoder, the sector selector, and the drivercircuit, referred to in FIG. I;

FIG. 4 is a pulse train diagram showing the sampling times and thesampling period of the pulses delivered to the multiplexer which in turnresult in the aforementioned low duty cycle;

FIG. 5 is a block and schematic diagram of the frequency dividingcircuit utilized to count down the frequency available from a crystaloscillator to 1 Hz also showing a pulse shaper and level translatorutilizing in matching the high frequency section of the device to thelow frequency section of the device;

FIG. 6 is a pulse train diagram showing the derivation of 41 (b and d)from intermediate outputs of the frequency dividing circuit shown inFIG. 5;

FIG. 7 is a block diagram of a binary seconds or minutes counterutilizing toggle-type flip-flops to indicate a binary numbercorresponding to integers between 0 and 59;

FIG. 8 is a block diagram of a counter circuit for indicating hours inbinary form in which toggle-type flipflops are utilized to represent inbinary form integers between 0 and II;

FIG. 9 is an expanded diagram of the multiplexer circuit shown inconnection with FIG. 3;

FIG. 10 is an expanded diagram of the decoder circuit shown inconnection with FIG. 3;

FIG. I] is an expanded diagram of the driver circuit shown in connectionwith FIG. 3;

FIG. 12 is an expanded diagram of the sector selector circuit shown inconnection with FIG. 3; and

FIG. 13 is a diagram showing the arrangement of the light emittingdiodes to be driven by the output of the driver and sector selectorcircuits shown in connection with FIGS. 11 and I2.

BRIEF DESCRIPTION OF THE INVENTION There is disclosed a logic anddriving circuit for a light emitting diode type horologic display inwhich three diodes are read out at any given time torepresent the timeof day. Power consumption is kept to a minimum by the use of a twovoltage level system with the lower voltage supplying those portions ofthe circuit working at a high frequency while the higher voltagesupplies the display and those portions of the driving circuit operatingat a considerably lower frequency. In addition to a crystal frequencystandard and a divideby-two flip-flop countdown circuit which provides a1 Hz signal to a series of toggle flip-flop counting circuits whichfunction as the seconds, minutes and hours storage elements, there isprovided a multiplexer coupled to the outputs of these counting circuitswhich is strobed with pulses having a combined duration of only afraction of the sampling cycle. This results in a low duty cycle for theoutput of the multiplexer and thus for the display itself whichconserves on the power necessary to drive the display. Since hour,minute and second information is sequentially sampled by themultiplexing circuit, multiplexing eliminates decoder and driverredundancy. Provision is made in the multiplexing logic for dividing thehorologi'c display into quadrants or sectors so as to further reduce thenumber of driver and decoder elements. As a result there is alsoprovided a quadrant selecting circuit. The sampling pulses for themultiplexing circuit are conveniently derived from the frequencystandard countdown circuit. The driving system utilizes complementarymetal oxide semiconductor (CMOS) components in which power drain isminimized because these elements draw appreciable power only whenswitching. A further power consumption advantage is obtained byutilizing NAND gate logic to permit the use of these low power CMOScomponents. Toggle flip-flops are chosen for the counters because theyare available in metal oxide semiconductor form and because the totalnumber of transistors utilized is reduced. The logic described herein isused with a horologic display in which the minutes and seconds aredisplayed in the single ring of elements with the hours being displayedin another single ring of elements.

DETAILED DESCRIPTION OF THE INVENTION As mentioned hereinbefore thesubject logic and driving circuit is tailored to a type of horologicdisplay in which the time of day is read out by three light emittingdiode elements. It will be appreciated, however, that many of theconcepts utilized in power conservation in the driving of this displaycan be equally well utili'zed in the driving of any XY addressabledisplay in which power consumption is a major factor. Thus, al-

though the subject logic and driving circuits are described inconnection with the horologic display in which the time of day isrepresented by two rings of light emitting elements, any system in whichpulses are provided on output lines of a driving circuit is within thescope of this invention.

Referring now to FIG. 1, a horologic display 100 is shown with an outerring 101 of 60 light emitting diodes, and an inner ring 102 of 12diodes. The time of day in this display is indicated by the sequentialactivation of the individual light emitting elements. In this display,minutes and seconds are represented by utilizing the same set of lightemitting elements. TI-Ie importance of representing time by using thesame light emitting elements for seconds and minutes is the saving of asmany as 60' light emitting elements. The display to which the subjectlogic is tailored therefore minimizes the number of light emittingelements by portraying minutes and seconds on the same ring by the sameset of elements. There are of course other ways of representing timeutilizing concentric rings of time indicating elements in whichmultiplexed readout of counters having binary outputs drives theseelements. In addition, for instance additional elements may be added toindicate half hour of 20 minute intervals. In the configuration showninvolving a set of 60 elements arranged so as to define a closedgeometric curve or ring 101, minutes are portrayed by sequentiallyactuating successive light emitting elements clockwise around the ring101 within on durations of 1 minuteQSimultaneously, each of the elementsin this ring are lit sequentially in a clockwise direction for onesecond such that at any given minute the seconds indications have beenstepped around the ring until they reach the 12 oclock position. At thistime the minute indication is stepped ahead so as to indicate the startof a new minute with the second indicator corresponding to the firstsecond of this new minute. The hours are represented by the concentricring 102 which are actuated sequentially having a 1 hour duration. Thetime indicated by the display as shown by the darkened light emittingdiodes 103, 104 and 105 is 1:12 and 39 seconds.

The driving circuit for display 100 generally consists of a frequencystandard indicated by oscillator and countdown circuit 115, whichproduces a precise 1 Hz signal. This signal is coupled through a leveltranslator to a second series of countdown circuits involving counters130, 131 and 132 which serve as storage elements for seconds, minutesand hours information. The output of these counters is in binary formsuch that the information contained in each one of these counters issequentially read out or sampled by a multiplexing cir' cuit 140. Thebinary information sampled by the multiplexing circuit is coupled to adecoding circuit which provides a pulse of one of 16 output linesdepending on the binary number stored in the particular counter read outby the multiplexing circuit 140. This pulse activates a driver circuitwhich in turn drives simultaneously all five of the sectors into whichthe display 100 has been divided. In addition, a portion of the outputof the multiplexer circuit drives a sector selector which selects whichof the aforementioned five sectors is to be enabled. The enabling ofonly one of the five sectors results in the activation of only one diodefor each sampling pulse to the multiplexer circuit 140. The inner ring102 of 12 diodes representing hours is in essence one sector which isactivated in the timed sequence determined by the multiplexer circuitsuch that when the hour counter is read out by the multiplexer circuit,the sector selector is directed to enable the hour sector. Theminutes-seconds ring 101 is divided into four sectors so that both thesector and the particular element in the sector must be driven to lighta particular element.

Referring to the oscillator 110, it is a crystal oscilla tor with thecrystal 111 having a frequency of 65, 636 Hz. This corresponds to 2 Hz.The output of the oscillator is coupled to a divide-by-two countdowncircuit shown diagrammatically in the dotted box 115. This is composedof a series of flip-flops shown diagrammatically at 116 which basicallydivide the output of the preceding flip-flop by two. Thus, by the use of16.individual flip-flops, the 2 Hz oscillator output is reduced to 1 Hz.There are however intermediate outputs from the countdown circuit whichare utilized for forming the sampling pulses for the multiplexer. Thesereadouts are tapped from the outputs of various of the flip-flops andrepresent respectively a 256 Hz signal, a 128 Hz signal, and a 64 Hzsignal. These intermediate signals are coupled to the pulse shaper andlevel translator I20 and thence to the multiplexer circuit 140 wherethey serve to cycle the multiplexer such that a sampling period takesone sixty-fourth of a second with the individual sampling timesoccupying in one embodiment only 12.5 percent of this one sixty-fourthsampling period. As mentioned hereinbefore, the high frequency circuitsare supplied with a lower voltage, thus conserving power. The highfrequency circuits are the oscillator circuit 110 and the countdowncircuit 115. In order to enable the use of the pulsed signals generatedby the countdown and oscillator circuits, there is of necessity a leveltranslator which makes the signals at the output of the countdowncircuit compatible with those of the multiplexer and the countercircuits 130, 131 and 132. The 256 Hz signal has a dual purpose insofaras it is utilized in forming the sampling pulses for the multiplexercircuit 140 and as speeds time setting signal. As can be seen, theoutput of the level translator 120, at least in one configuration, is a1 Hz signal designated Y, and a 256 Hz signal designated by the letterZ. In ordinary operation the switch 136 is in the position showncoupling the counters 130, 131 and 132 to the 1 Hz signal. If, however,it is desired to change the time displayed by the subject horologicdisplay, switch 136 is coupled to a higher frequency signal, in thiscase the 256 Hz signal, which peeds up the counting operation until theappropriate time is reached at which point switch 136 is returned to theposition shown in FIG. 1. This 1 Hz output signal is coupled directly tothe seconds counter 130 which operates in such a manner as to count thenumber of bits of information delivered thereto between and 59 (i.e., 60bits). The state of the counter is indicated by a binary output of 6bits as shown by the output lines 133. In the configuration shown, thestate of the counter is changed on the negative going edge of anincoming pulse. What this means is that the flip-flops used in thecounters are set by the leading edge of an incoming pulse and aretoggled by the trailing edge. After 59 bits have been counted; secondscounter 130 resets and also simultaneously delivers a first pulse to theminutes counter 13]. Minutes counter is identical to the seconds counterin that it has 6 flip-flops. Thus its state is also represented by abinary number of 6 bits. The output in binary form of the minutescounter 131 is shown by the output lines 134. Thus, the seconds counter130 must cycle through all of its 60 bits before the minute counterreceives its first pulse. Likewise, the minute counter must cyclethrough its 60 bits before the hour counter 132 receives its firstpulse. The hour counter is provided with four flip-flops and thus itsstate is represented by the four output lines 135. At the end of 12 bitsthis counter is reset. It will be appreciated that counters 130 and 131have six flipflops each. It is therefore possible for these counters tocount up to 63 in binary form. However, these counters are reset afterthey reach a count of 59 by a logic to be described hereinafter.Likewise, counter 132 can count up to 15. However, this counter is resetafter it reaches a count of I], thus representing 12 bits. Thesecounters, as mentioned hereinbefore, are constructed of toggle-typeflip-flops with attendant NAND gate logic circuitry to make the countersoperate in the above fashion. They are toggle-type flip-flops ratherthan J K-type flip-flops because toggle-type flip-flops use lesstransistors in the form shown than do .IK flip-flops. As has beenmentioned hereinbefore that the available of these devices in MOS formcontribute significantly to power consumption reduction. It will beappreciated that there is an analog in the JK flip-flop counter art tothe toggle flip-flop once the NAND gate-inverter logic shown inconnection with FIGS. 7 and 8 is known. Also, any binary encoderswhichcount pulses and generate a binary output can be used with themultiplexer.

In the configuration shown, the information in binary form is availableat outputs 133, 134 and 135 which are coupled to the multiplexer circuit140. The multiplexer circuit is basically a coincident gate-type circuitsuch that when enablingpulses 5 or (1 appear, either the seconds counteror the minutes counter or the hours counter is read out to both thedecoder unit 150 and the sector selector 170. (1) and 4),, are generatedfrom outputs of the countdown circuit by the pulse shaping portion ofthe level translator 120. After tb d) and :11 are generated, they arelevel translated by level translator so as to be compatible with themultiplexer circuit which generally operates at 3 volt level as opposedto the 1.5 volts supplied to the high frequency circuits mentionedhereinbefore. and d) are not however coextensive with the outputs of thevarious flip-flops from which they are derived. As will be discussed inFIG. 5, the outputs of the three selected flip-flops from which (it11),, and 15 are derived are coupled to NAND gate circuitry such that aseries of three sequential pulses are produced spaced apart byconsiderable dead air time. (b 4),, and (b are coupled to themultiplexer 140 to cause the multiplexer to sample the outputs of thecounters in mutually exclusive and separated time intervals within thesampling cycle. The sampling takes place only over the time at which (1)41 and 4),, appear. This results in the seconds counter being read outduring the duration of the pulses da the minutes counter being read outduring the duration of the pulse 4) and the hour counter being read outduring the duration of the pulse (1) At all other times the output ofthe multiplexing circuit is a binary coded set of words which areincapable of actuating any light emitting diodes in the display. Thuswhen the term low duty cycle is used it refers to the fact that thelight emitting diodes have a low duty cycle. In actuality none of theother components in the system are inhibited during dead air time." Itis sufficient that only the display has the low duty cycle since itdraws the majority of the power. In one embodiment the sampling time forone pulse is only 12.5 percent of the entire sampling cycle. If threesamples (i.e. (1: and (1) are made during the sampling cycle thesampling pulses take up only 37.5 percent of the sampling period.

As mentioned hereinbefore the output of the multiplexer in addition tobeing coupled to the decoder which decodes either the seconds, minutesor hours numbers, is also coupled to the sector selector 170. It will beappreciated that the aforementioned ring of 60 elements is divided intofour parts or sectors. These parts are, however, not equal for reasonswhich will be described hereinafter. At this point it is only necessaryto note that the sector selector is activated by the last two bits ofinformation from either the seconds counter or the minutes counter. Thehours sector is activated merely by a pulse appearing on the line 41,,since it is completely separate from the other four sectors utilized toactivate the outer ring of elements. However, the outer ring of elementsbeing divided into four parts must be actuated in some orderly mannerdepending on the numbers in the seconds and minutes counters. The sectorwhich these numbers occupy is conveyed to the sector selector as thelast two bits of information in each one of these counters. These lasttwo bits of information in conjunction with d) and dz instruct thesector selector in which sector the information being read out by themultiplexer 140 is to be placed. Thus, although there are 60 elements inthe outer ring 101, the driver need only have 16 outputs as shown inFIG. 1. These 16 outputs are connected in parallel to correspondingelements in each one of the first three sectors. The fourth and hoursectors however have only 12 elements and therefore only the first 12 ofthe output lines of the driver are connected in parallel tocorresponding elements both in sectors I-III and the fourth and hoursectors. Actually, the fourth sector is designated sector No. II inkeeping with quadrant" designation commonly used in analytic geometry.

' Neglecting for the moment the hours activation, the minutes and secondactivation is accomplished by the use of only 16 driving lines and fourquadrants making this akin to an XY addressable array. If, for instance,10 minutes past the hour is to be represented,

during the minutes segment of the multiplexing, quadrant I is enabled bygrounding it, while the binary number corresponding to 10 is decided bythe decoder 150. The decoding circuit enables a section of the driver160 which then connects to V one electrode of corresponding elements No.10 in each of the sectors. Thus V is fed in parallel to the element No.10 in quadrant" I, the element No. 10 in quadrant II, the element No. 10in quadrant III, and the element No. 10 in quadrant IV. However, sinceonly quadrant" I is grounded, diode No. 10 in quadrant I is the onlydiode which is connected between V and ground.

Outputs zero through 11 of the driver 160 are also coupled to the innerring of elements 102 such that the No. l element is also connected to Vvia output line 10. However, since only quadrant l is activated, thedelivery of this pulse to this element has no effect. However, ifo'clock is to be represented, then the hour sector is grounded inconjunction with the connection of V to the No. l0 element via outputline 10. This causes the 10th diode in the inner ring 102 to become litduring that portion of the multiplexer sequence which reads out thenumber l0 contained in binary form in hour counter I32. Thus, it can beseen that the sector selector 170 is only necessary to distinguishbetween seconds readouts and minutes readouts with the hours readoutsbeing directly actuated by is shown to pass directly through the sectorselector 170. As mentioned hereinbefore the minutes and seconds readoutis a bit more complicated. During the time when the seconds are readout, the last two bits in the seconds counter instruct the sectorselector 170 to actuate the appropriate quadrant." When it becomes timefor the minutes counter to be read out, the multiplexer also instructssector selector 170 which quadrant is to be actuated. However, since thehours are not segmented in any form there is no necessity to instruct asector selector which quadrant to actuate because there is only onesector as far as the hour light emitting diodes are concerned. It willbe appreciated that there are five sectors, with the first four sectorsdesignated as quadrants so as to distinguish outer ring actuation fromthat of the inner ring.

The matter of actuation of this subject display is described inconnection with FIG. 2. In this diagram, the minute-second portion ofthe display is divided up into four quadrants as shown. The firstquadrant has 16 light emitting diode elements associated with it. Theserun from positions zero through 15. Going clockwise the fourth quadrantalso has 16 elements going indicated from positions zero through 15 asdoes the third quadrant. The fourth quadrant however has only I2elements which run from positions zero through 11. This asymmetricdivision of the of the elements is indicated by the particular seconds,minutes and hours counters employed. It is of course possible to useother types of counters such that the quadrant" representation is madesymmetrical. However, if symmetrical quadrants are used more complicateddecoders and more complicated counters are necessary. It will beappreciated that the asymmetrical division of quadrants described ischosen because it greatly simplifies the logic circuitry required. Forexample, if four equal quadrants" of 15 elements each are employed witha 6 bit 0-59 counter, counter outputs 16, 31 and 47 would not be decodedalthough they are states of the counter which exist during each cycle.Thus, an error of 3 units per cycle would be introduced. To circumventthis problem four 0-l4 counters could be used instead of one 0-59counter for seconds and minutes. This would require 16 flip-flopsinstead of 6 flipflops as described herein. The outputs from driver ofFIG. 1 are shown to the bottom left-hand side of diagram shown in FIG.2.It will be appreciated that the outputs from the driver 160 areconnected in parallel not only to those corresponding elements in eachone of the quadrants," but also to the corresponding element in the hourring (hour sector). Thus, the zero output line is connected to thequadrant I zero, the quadrant II zero, the quadrant III zero, and thequadrant IV zero as well as to the hour sector zero which in this caserepresents the hour of 12 oclock. Likewise, for instance, the llthoutput is coupled simultaneously to the llth element in the firstquadrant, the l lth element in the second quadrant," the l lth elementin the third quadrant, and the l lth element in the fourth quadrant. Itis also connected to the l lth element in the hour ring (hour sector).Output lines 12 through 15 are however only connected to thosecorresponding elements in quadrants" I, III and IV. It will be obviousthat there is no element for them to be connected to in quadrant" II orin the hour ring sector. As mentioned hereinbefore, the hourring isrepresented by a single sector which is driven oractuated during thehour readout portion, dz of the multiplexing cycle. However, for theseconds and minutes readout the quadrants" I, II, III and IV are readout in accordance with the binary number in the seconds or minutescounter which is activated or read out by the multiplexer 140. Thus,there are only three light emitting diodes read out in a given samplingcycle. In the embodiment shown in the Figures, the minute, second andhour are read out once every one sixty-fourth of a second or 64 times asecond. This provides for a seemingly continuous readout of the lightemitting diode display. It is however not continuous since the samplingcycle takes place over one sixty-fourth of a second and the actualreadout takes place over only 12.5 percent of the cycle. Thus the diodesin the display are lit for only 12.5 percent of the time. This 12.5percent figure in conjunction with the one sixty-fourth of a secondsampling rate provides the user with what appears to be a continuousreadout of a time period in excess of one year. It will be appreciatedthat other acceptable duty cycles are feasible going as low as 1.56percent and as high as 25 percent.

The logic involved in the subject system is now described in general. Asmentioned hereinbefore, each of the aforementioned counters 130 through132 have an output in binary form. The output for the seconds counter130 is in the form of 6 bits designated A through F The binary output ofthe minutes counter 131 is designated A through F and the output of thehours counter is designated A through D For reference the correspondingbinary number table of through 63 is now presented.

TABLE I No. FEDCBA No. FEDCBA 0 O 0 0 0 0 0 32 l 0 O 0 0 0 1 0 0 0 0 0 133 l 0 0 0 0 1 2 0 0 O 0 l 0 34 l O 0 0 1 0 3 0 0 0 0 1 l 35 1 0 0 0 l l4 0 0 0 l O O 36 l 0 0 l O 0 0 O 0 l 0 l 37 l 0 0 l O l 6 0 0 0 1 1 0 381 0 0 1 1 0 7 0 0 0 l l l 39 l 0 0 l 1 1 8 0 0 1 0 0 0 40 l 0 l 0 0 0 90 0 l 0 0 1 41 l 0 l 0 0 1 l0 0 0 1 0 l 0 42 l 0 l 0 1 0 11 O 0 1 0 l l43 1 O l 0 l 1 12 0 0 l l 0 0 44 l 0 1 l 0 0 l3 0 0 1 1 0 1 45 l 0 l l Ol 14 0 0 1 l l 0 46 1 0 l 1 1 0 l5 0 0 1 l 1 l 47 l 0 l l 1 1 l6 0 1 0 00 O 48 l l 0 O 0 0 l7 0 l 0 0 0 l 49 1 l l 0 0 1 l8 0 l 0 0 l 0 50 1 l O0 1 0 l9 0 l 0 0 l 1 51 l l 0 0 l l 0 l 0 l 0 0 52 l l 0 1 0 0 2| 0 l 01 0 l 53 1 l 0 1 0 l 22 0 l 0 l l 0 54 1 l 0 l l 0 23 0 l 0 l l l 55 1 l0 l l l 24 0 l l 0 0 0 56 l l l 0 0 0 0 1 l 0 O l 57 1 l l 0 O l 26 O ll 0 l 0 58 l l 1 0 l 0 27 O l l 0 l l 59 1 l l 0 l l 28 0 l l l 0 0 6O 1l 1 l 0 0 29 0 l l l 0 l 61 l 1 l l 0 1 Not 0 l l l l 0 62 l l l l l 0Used 3| 0 l l 1 1 l 63 l l 1 l l 1 As shown at the bottom on FIG. 3, theoutputs of counters 130 and 131 and 132 are coupled to the multiplexercircuit 140. In general, each of the corresponding outputs of each ofthe counters is connected as shown in the multiplexer circuit to threecorresponding NAND gates 141, 142 and 143. The outputs of these NANDgates form the inputs for a further NAND gate 144. Positive true" logicis used in this system (i.e., a logic 1" is represented by a positivevoltage potential approximately equal to the supply voltage whereas alogic 0" is represented by an approximately zero voltage potential). TheNAND gate produces a logic high or 1" output if one or more of itsinputs are low. A logic low is generated if, and only if, all of theinputs are high. Taking, for instance, the A output from each of thecounters (A A A each of these form one of the inputs for theaforementioned NAND gates 14] through 143. The other input for each ofthe NAND gates 141 through 143 is the sampling signal which permitsreadout of the particular counter. For instance, if it is desired thatthe seconds be read out a logic 1 signal 4),,- is applied simlutaneouslywith the A, signal to NAND gate 141. If A is a logic 1 signal, thecoincidence of the 42 and the A signal results in a logic 0 signal AThis signal is coupled to NAND gate 144 such that a logic 1 output ofgate 144 indicates the simultaneous presence of an A logic 1 signal andthe tb signal. NAND gate 144 produces this logic 1 signal because theother signals to this NAND gate will be logic 1" during the presence ofa sampling pulse. Thus during sampling only one signal from gates141-143 will be low. This is the condition ofa logic l output from NANDgate 144. The same is true for the minutes sampling signal 1b,, and thehours sampling signal (b It can be seen therefore that the multiplexerutilizes coincident-gate sampling. The multiplexer section shown in FIG.3 is but one of many such sections corresponding to the six outputs fromthe seconds and minutes counters and the four outputs of the hourscounter. The output of gate 144 is a logic level signal which indicatesthe simultaneous presence of either A S and (1, or AM and rim, or A and(b signals. There is also provided in the multiplexer an invertercircuit 145 which produces the complement of that which is produced atthe output gate 144. The analysis of the multiplexer circuit is a directconsequence of demorgans laws.

The output of the multiplexer circuit is coupled to the decoding circuitwhich in general is a simple circuit involving 16 NAND gates. One ofthese gates is represented by the reference character 151 to be thatcorresponding to the A, B, C', D outputs of the multiplexercorresponding to the A, B, C and D outputs from a counter. The primeafter these letters indicates that these are in fact sampled. In otherwords, there is either a 45 a 4) or 4a,, which enables the informationA, B, C, and D to be read out. Referring to Table l, the presence oflogic 1s" in A, B, C, and D represent the number 15, the number 31, andthe number 47. the selection of which of these numbers is represented bythe display is accomplished by the sector selector 170. lgnoring for themoment the hours indications since this number does not exist on thehours ring, the input to the sector selector is two fold. The firstinputs are the enable inputs, and 4) These are coupled to inverters 171and 172 such that the output thereof is HT and a; (i.e., logic 0s).Utilizing a further NAND gate 173 its output is a logic 1 when 41 or4a,, are present at inverters 171 and 172. Thus whenever or 4; ispresent the "quadrant" portion of the sector selector is enabled. Thismeans that there is a logic 1 signal at one of the inputs to NAND gate174. The output of gate 173 is thus an input to gate 174 which is also aNAND gate. The other two inputs to this gate are the E and F outputsfrom the multiplexer circuit and thus correspond to the sampled E or Foutputs from the minutes and seconds counter. In this case the F outputof the counter is a logic 0. This is recognized by the multiplexer whichgenerates a logic 1" signal on its 1 output line. The multiplexergenerates logic 1 signals indicating a logic 0 signal from a counter.Thus all Y signals referred to herein are available as logic 1 signalsfrom the multiplexer. E and F indicate that a logic 1 exists a t NANDgate 174. With three logic "1 signals (E', F, (b) the output of gate 174is low.

This is converted to a high signal by inverter 175. This logic highsignal then renders NPN tran sistor 161 conductive. From Table I thepresence EF indicates that the number 31 is to be selected over thenumber 15 and the number 47. To reiterate, the output of the NAND gate174 in combination with the inverter circuit 175 indicates that there isa sampling of either the seconds or the minutes counter, and that thequadrant indi eating the number 31 should be activated. This quadrant,"referring to FIG. 2, is quadrantTlV. A logic 1 signal therefore from theoutput of inverter 175 is delivered to the base of the NPN transistor161 in the driver circuit 160. This particular NPN transistor is coupledbetween one electrode of each of the light emitting diode devices 162 ofquadrant" IV and ground. The other electrode of these light emittingdiodes is connected to the collectors of PNP transistors 163 whoseemitters are connected to V 3 volts. The output of the decoder gate 151is coupled simultaneously to the base of those transistors coupled tocorresponding light emitting diodes in each quadrant. Thus a logicgenerated by the presense of A", B, C, D at NAND gate 151 is coupled tothe base of transistor 163' at the same moment that a logic l isdelivered to the base of transistor 161. Thus the LED 162' is connectedto both V and ground.

For any given state of the decoder 150 and the sector selector 170, onlyone diode is actuated or lit. The results in the aforementioned low peakcurrent drain and the feasibility of using low cost high impedancebatter- Referring now to the hours actuation, the presence of 4),, atthe base of transistor 165 enables all of the light emitting diodes 166in the hour ring. If, for instance, the decoder gate corresponding to F,1?, G and I? were actuated, corresponding to a count in the hourscounter of 0000, then at sampling time the diode representing 12 oclockwould be lit. This is because the particular decoder gate produces alogic 0 signal when logic I signals A, E 3 and occur at the NAND gate inthe decoder. All of the other gates have logic 1 outputs. The gating inthe driver circuit simply renders conducting the transistors on eitherside of the light emitting diode which is to be actuated. The diode istherefore connected between a 3 volt power supply and ground through theNPN and PNP transistor across which it is connected in series. Variousbiasing resistors 167 are provided to complete the partial schematicdiagram of the driver circuit 160 shown in FIG. 3.

Referring now to FIG. 4, it will be apparent that the entire multiplexercircuit operates on the principle of coincident gating. However, thesampling period is dietated by the length of the sampling pulses, tb titand d) The length of the sampling pulses is considerably reduced bynarrowing these pulses. Since the output of the multiplexer circuit 140actuates the display, only during the presence of a sampling pulse, bynarrowing the sampling pulses the output of the multiplexer can bemaintained at a zero level for a considerable portion of time. As shownin FIG. 4, in one embodiment the samepling cycle is one sixty-fourth ofa second as shown by the distance between the leading edges ofconsecutive pulses 180 and 181 of the s sampling pulse train. However,the combined? widths of pulses 180, 182 and 183 only occupy about 12.5percent of the one sixty-fourth second time period. The duty cycle forthis logic and driving system is therefore defined to be the combinedpulse widths of the seconds, minutes and hours sampling signals ascompared with the length of time between the leading edges of twoconsecutive tps sampling pulses. Since the ouput of the multiplexer doesnot actuate the display for approximately 87.5 percent of the time, thedecoder circuit, sector selector circuit and the driver circuit areactuated for only 12.5 percent of the time that the display is running.Thus, the light emitting diodes are actuated for only 12.5 percent ofthe time that the display is running. Since NAND gate circuitry isutilized, and since complementary metal oxide semiconductor devices areutilized, the power saving with the circuit thus described in general,is considerable.

A more detailed description of the operation of the preferred embodimentof this invention is now described in detail in connection with FIGS. 5through 13.

Referring now to FIG. 5, an expanded diagram is shown in which thesignals 42 41 4) Y and Z are derived. Included in dotted box are thelast nine of the flip-flops in the countdown circuit 115. As can beseen, these are labeled F/F through FIF Each flipflop has two outputs.The first being a 6 output, and the second being the Q output. Asmentioned hereinbefore, the output of F/F, is a 1 Hz signal. Since thecountdown circuit 115 is supplied with a 1.5 volt potential, the outputQ, must be converted to be compatible with the 3 volt follow-on systems.In order to accomplish this, the 0, output is coupled to the base of anNPN transistor 121 in the pulse shaping and level translating circuit120. When transistor 121 is ofi, the voltage at point 122 is high sinceno current is being pulled through this transistor. This voltage thencorresponds to the 3 volt potential at point 123. When, however, Q, isapplied to the base of transistor 121 as a logic high, transistor 121goes into conduction pulling the point 122 low by the IR drop across theresistor 124. Thus the output Y is an inverse replica of the output 0,.This same procedure is used for the time set output Z enclosed in dottedbox 125. Here the transistor 121' is coupled to the Q output of F/F Whenthe Q output of FIF is high, 122' is low because of the voltage dropacross the resistive element 124'. The time set signal is equal to 256Hz which in the worse case can reset the clock in about 6 minutes. Itwill however be appreciated that the tap for the base of transistor 121'can be taken off a higher numbered flip-flop such that the frequency ofthe signal at Z is increased proportionately thereto. The signals tb d)and d) are derived from the Q Q 2 Q and 1 outputs of flipflops 116 asfollows. As shown, the Q, output of HE, is coupled to one of the inputsof each of NAND gates 126, 127 and 128. The 6,, outputof F/F is coupledto another of the inputs to NAND gate 127. The 0,, output of F/F iscoupled to another of the inputs of NAND gates 126 and 128. The 6,output of F/F, is coupled to the last of the inputs to NAND gate 128while the Q, output of F/F is coupled to the last of the inputs to NANDgates I26 and 1 27. The outputs of these NAND gates drive the basesoftransistors 121", 121", and 121"" respectively. The boolean algebraicexpressions for the outputs of NAND gates 126 through 128 are as shown.By going through demorgans theorem recognizing the properties of thelevel shifting transistors 121, da dz and'qm are generated as shown inFIG. 6 having been derived from the outputs of FlF F/F and F/F,. Theremaining resistors 119 are for biasing purposes. It will be appreciatedthat the pulse widths of tb 4) and d) are equal to that of Q but therepetition rate is equal to that of 0,. Thus the combined pulse widthsof tb d) and d) are only 37.5 percent of the period of 0,.

Referring now to FIG. 7, the seconds/minutes counter is shown in dottedoutline. The toggle flip-flops described herein require two trigger (orclock) pulses which are out of phase T andT The flip-flops trigger(i.e., change state) upon the transistion of the T input pulse from ahigh to a low state. The toggle flipflops employed require only 17 MOStransistors per flip-flop which is about one-half the transistorsrequired for a JK flip-flop. Thus, while more NAND gates and invertersare necessary to make a counter (0-59) or (0-l) with toggle flip-flopsthan JK flip-flops, the total numbers of transistors required for acounter may be less with toggle flip-flops. It should be notedthrough-out the following discussion of the operation of the countersthat the first pulse is the 0th pulse and the 59th pulse thereforerepresents a count of 60. Likewise, in the hours counter the llth pulserepresents a count of 12. This agrees with the boolean Table I. Taking,for instance, this counter as the seconds counter 130, it is composed ofsix toggle flip-flops 138 labeled A, B, C, D, E, and F respectively. Itis the purpose of this counter to store the number of pulses received offrom zero through 59. If it were the purpose of this counter torecognize zero through 63 incoming pulses, the toggle flip-flops wouldbe cascaded in the normal manner, and no additional logic elements (NANDgates and inverters) would be required. How ever, in order to stop thetoggle flip-flop count at a point corresponding to the 59th incomingpulse and to reset it after this 59th incoming pulse requires the use ofNAND gate logic coupled with the inverters as shown. This NAND gatelogic assures that the outputs of the six flip-flops are all reset tozero on the trailing edge of the 59th pulse. The system for limiting thecount of this counter centers around the use of four NAND gates and fourinverter circuits. The input to the counter is the 1 Hz Y signal acrossthe switch 136 which goes directly to the T input of flip-flop 138A. TheY signal is inverted by the inverter 137 and is then coupled to the Tinput of this first toggle flip-flop. The outputs of the first toggleflip-flop (138A) are coupled directly to the inputs of the 13813 toggleflip-flop. Thereafter the switching theory becomes indeed complicated.Referring to Table l, and remembering that the flip-flops toggle on thenegative going edge of a pulse it will be appreciated that in theseconds/minutes counter, if the counter is allowed to run up past 59counts, nothing needs to be done about inhibiting the input toflip-flops 138A and 1388 because the change from 59 to 60 is the same asa change from 59 to zero (i.e., the outputs of flip-flops 138A and 1388will be the required zero" after the 59th pulse has passed). The 138Ccounter after the 59th pulse would ordinarily go to a logic l." Sometype of circuitry is therefore needed to maintain the output offlip-flop 138C at its zero level (no toggle). The inputs to flip-flop138C are therefore inhibited during the passage of the 59th pulse sothat the trailing edge of the 59th pulse does not toggle flip-flop 138C.The passage of the 59th pulse is indicated when D, E and F are all logicls" and B goes from a high to a low. D, E, and F are thence the inputsto a NAND gate as shown by 139. An output low from gate 139' indicatesthe presence of D, E and F at its inputs as logic ls. This output low(i.e., logic 0 is coupled to one of the inputs of a NAND gate 139". Theinput to flip-flop 138C is ordinarily the B output of flip-flop 1388.What is done in effect is to inhibit this B output of flip-flop 1388from reaching the input to flip-flop 138C when D, E, and F are presentat the output of their respective flip-flops and when B goes from alogic 1 to a logic 0." From the first table, D, E, and F are logic lsfrom 56 through 59. However, during this interval B only goes from ahigh to a low after the 59th pulse. The fact that B goes from a low to ahigh does not trigger the 138C flip flop. The toggle flip-flop onlychanges state when its input goes from a logic high to a logic low (thenegative going edge of a pulse). Therefore, the only time at which theinput to 138C is inhibited is after the 59th pulse input. The T input toflip-flop 138C is therefore the output of inverter 146' (i.e., B DEF).The output of gate 139' (BDEF) is thence coupled to the T input offlip-flop 138C to complete the toggling.

At the passage of the 59th pulse flip-flops D, E, and F would notnormally change state and would be logic 1. it is therefore necessary inorder to return the counter to the 000000 first state to causeflip-flops D, E, and F to toggle. Since these flip-flops are cascaded,it is only necessary to toggle the D flip-flop in order to toggle E andF flip-flops back to the original D=0, E=0, and F=0 state. This isaccomplished as follows: Normally flip-flop 138D toggles in response tothe output of flip-flop 138C changing from a logic 1" to a logic 0".This is because the output of 139"" goes low on the appearance of alogic l pulse at the 6 output of the 138 flip-flop. However, flip-flop138D is made to toggle either on the E input to gate 139"" or on anABDEF condition since the ABDEF condition occurs only on the 59th pulseon the 60th pulse. A and B change to a zero which causes the output of139"to go high. This causes the output of 139"" to go low, thus togglingthe flip-flop 138D. Therefore, flip-flop 138D while not ordinarily beingtoggled after the 59th pulse is in fact toggled so as to return thecounters 138D, 138E, and 138F to a zero state. The ABDEF signal isderived as follows: The output of NAND gate 139' is is? This is invertedto DEF by inverter 146". The output of the inverter 146" is an input toNAND gate 139". A and B signals from flip-flops 138A and 1388 form theother two inputs to NAND gate 139". The output of NAND gate 139" is lowwhen ABDEF signals are present at their respective flip-flops. Theoutput of NAND gate 139" is thus m. This is coupled as one of the inputsto NAND gate 139"" along with a 6 input. The 6 input normally togglesflip-flop 138D. The presence of the ABDEF condition indicates thepassage of the 59th pulse. Since the 59th pulse is indicated by ABDEF,going from ABDEF to ABDEF indicates passage of the 59th pulsev Theoccurrence of ABDEF is sensed by an output from gate 139" which togglesflip-flop 138D. The output of gate 139" is inverted by inverter 146' toform the T input to flipflop 138D, and is inverted again by inverter146"" to form the T input for this flip-flop.

The output of the seconds counter (output F from flip-flop 138F) isconnected to the input of the minutes counter. The minutes counteroperates in precisely the same way as the seconds counter in that bothcounters

1. Apparatus for displaying the time of day comprising: a timeiNdicating display having a plurality of time indicating elements, eachelement having two electrodes and being actuated by the application of apotential across these electrodes, said display containing a firstnumber of time indicating elements in a first ring representing bothminutes and seconds and a second number of time indicating elements in asecond ring representing hours, the elements being divided into groups,one electrode of all the elements in each group being interconnected soas to form a group terminal, the other electrodes of the elements ineach group being interconnected with the other electrodes ofcorresponding elements in the other groups to form a position terminal;means for generating a pulsed electrical signal; means responsive tosaid pulsed electrical signal for generating a binary outputrepresenting time; means for decoding said binary output and for drivingsaid display in accordance with said decoded output; and meansinterposed between said means for generating said binary output and saiddecoding means, for multiplexing said binary output such that onlyportions thereof are coupled to said decoding means during any one time,said multiplexing means sampling said binary output portionssequentially over mutually exclusive and spaced time intervals, suchthat said display is driven only when said binary output is sampled,whereby said multiplexing means not only functions to sequentiallysample portions of said binary output, but also serves to drive saiddisplay in a low duty cycle mode.
 2. Apparatus as recited in claim 1wherein said binary output contains information concerning the group aswell as the position of the element to be actuated, said decoding meansdecoding this group and position information and causing said drivingmeans to apply said potential across that element which is located atthat position in that group that is indicated by that portion of saidbinary output which is sampled by said multiplexing means.
 3. Theapparatus as recited in claim 2 wherein said means for generating apulsed electrical signal is powered with a lower voltage than that ofthe rest of the apparatus to conserve on power.
 4. Apparatus for drivinga time display having a number of time indicating elements actuated bythe application of a potential across the electrodes thereof, comprisingin combination: means for generating a series of pulsed electricalsignals, each signal having a precise frequency, and one of said signalshaving a frequency of 1 Hz; a power supply; means operative in responseto the signals generated by said pulse generating means for generating aseries of seconds, minutes and hours sampling pulses in a timedsequence, said series of sampling pulses repeating over a predeterminedsampling period and having sampling durations totalling only a fractionof said sampling period; pulse-to-binary encoding means for storing inbinary form information derived from said 1 Hz signal corresponding toseconds, minutes and hours, said encoding means storing said binaryinformation such that said seconds and minutes information hasassociated with it bits of information indicating that minutes andseconds are divided into a predetermined number of sets each having anumber of elements some of which corresponding in position to elementsin other of said sets, said encoding means providing binary outputsignals corresponding to said seconds, minutes and hours information andto the set to which said information belongs; multiplexing means forcoupling said binary output signals to corresponding outputs thereofsuch that the seconds, minutes, hours and set information stored in saidpulse-to-binary encoder is read out in response to the presence of acorresponding sampling pulse at said multiplexing means, saidmultiplexing means producing signals capable of actuating elements insaid display only during the presence of a sampling pulse at the inputthereto; meanS for decoding the binary output of said multiplexing meansso as to form an output signal in one of a predetermined number ofoutput circuits within said decoding means; means active in response toa signal in one output circuit of said decoding means for selectivelyconnecting one electrode of those time indicating elements having thesame position in their respective sets to one terminal of said powersupply, the elements to be connected to said one terminal being selectedby that binary state of said multiplexing means corresponding to thatbinary state of said encoding means read out by said multiplexing meansduring a given sampling pulse interval; and means responsive to thatinformation in said encoding means read out by said multiplexing meansduring said given sampling pulse interval indicating the set to whichthe encoding means output belongs for connecting to the other of theterminals of said power supply those other electrodes of the timeindicating elements corresponding to this set, whereby individual timeindicating elements are sequentially actuated in accordance with saidseries of sampling pulses by being connected across said power supplyover a low and therefore power-saving duty cycle determined by saidsampling pulse duration in combination with said multiplexing means. 5.The apparatus as recited in claim 4 wherein the same time indicatingelements indicate minutes and seconds.
 6. The apparatus as recited inclaim 4 wherein the number of time indicating elements indicatingminutes and seconds exceeds the number of output circuits in saiddecoding means.
 7. Apparatus for driving a time display having a numberof time indicating elements actuated by the application of a potentialacross the electrodes thereof, comprising in combination; means forgenerating a series of pulsed electrical signals, each signal having aprecise frequency, and one of said signals having a frequency of 1 Hz; apower supply having a pair of low voltage output terminals and a pair ofhigh voltage output terminals, said low voltage output terminals beingcoupled to said pulse generating means; means operative in response tothe signals generated by said pulse generating means for level shiftingsaid 1 Hz signal to a level compatible with the remainder of saidapparatus and for generating a series of seconds, minutes and hourssampling pulses in a timed sequence, said series of sampling pulsesrepeating over a predetermined sampling period and having samplingdurations totalling only a fraction of said sampling period;pulse-to-binary encoding means for storing in binary form informationderived from said level-shifted 1 Hz signal corresponding to second,minutes and hours, said encoding means storing said binary informationsuch that said seconds and minutes information has associated with itsbits of information indicating that minutes and seconds are divided intoa predetermined number of sets each having a number of elements some ofwhich corresponding in position to elements in other of said sets, saidhour information constituting an undivided further set having a numberof elements, said encoding means providing binary output signalscorresponding to said seconds, minutes and hours information and to theset to which said information belongs; multiplexing means for couplingsaid binary output signals to corresponding outputs thereof such thatthe seconds, minutes, hours and set information stored in saidpulse-to-binary encoder is read out in response to the presence of acorresponding sampling pulse at said multiplexing means, saidmultiplexing means producing signals capable of actuating elements insaid display only during the presence of a sampling pulse at the inputthereto; means for decoding the binary output of said multiplexing meansso as to form an output signal in one of a preselected number of outputcircuits within said decoding means; means active in response to asignal in one oUtput circuit of said decoding means for selectivelyconnecting one electrode of those time indicating elements having thesame position in their respective sets to one high voltage outputterminal of said power supply, the elements to be connected to said oneterminal being selected by that binary state of said multiplexing meanscorresponding to that binary state of said encoding means read out bysaid multiplexing means during a given sampling pulse interval; andmeans responsive to that information in said encoding means read out bysaid multiplexing means during said given sampling pulse intervalindicating the set to which the encoding means output belongs forconnecting to the other of the high voltage output terminals of saidpower supply those time indicating elements corresponding to this set,whereby individual time indicating elements are sequentially actuated inaccordance with said series of sampling pulses by being connected acrossthe high voltage terminals of said power supply over a low and thereforepower-saving duty cycle determined by said sampling pulse duration incombination with said multiplexing means and whereby only low frequencyelements in said apparatus are connected to said pair of high voltageoutput terminals.
 8. The apparatus as recited in claim 7 wherein thesame time indicating elements indicate minutes and seconds.
 9. Theapparatus as recited in claim 7 wherein the number of time indicatingelements indicating minutes and seconds exceeds the number of outputcircuits in said decoding means.
 10. The apparatus as recited in claim 7wherein said binary encoding means is a series of three cascadedcounters, the first two of said counters having six toggle flip-flopsand the third counter having four toggle flip-flops, the first two ofsaid counters counting from 0 through 59 bits of input information, saidfirst two counters being reset after the 59th bit, said third countercounting from 0 through 11 bits of input information and being resetafter said 11th bit.
 11. The apparatus as recited in claim 10 whereinall switching components in said apparatus are metal oxidesemiconductors.
 12. The apparatus as recited in claim 11 wherein saidcounters utilize NAND gate logic for resetting.
 13. The apparatus asrecited in claim 11 wherein said means for generating sampling pulses,said counters, said multiplexing means, said decoding means, and saidmeans responsive to set information utilize NAND gate logic inperforming their various functions.
 14. The apparatus as recited inclaim 10 wherein said time indicating elements are arranged in twoconcentric rings with a first number of time indicating elements in afirst ring representing both minutes and seconds and with a secondnumber of time indicating elements in a second ring representing hours,the elements being divided into said sets, one electrode of all theelements in each set being interconnected so as to form a set terminal,the other electrodes of corresponding elements in each set beinginterconnected so as to form a position terminal, said multiplexingmeans, said means for decoding, said means for selectively connectingone electrode, and said means responsive to set information acting incombination to apply a potential across a selected element bysimultaneously applying a potential to a selected set terminal and aselected position terminal so as to successively actuate each of theelements in said first ring during successive seconds, each of theelements in said first ring during successive minutes, and each of theelements in said second ring during successive hours.
 15. The apparatusas recited in claim 14 wherein said elements are divided into five setswith three sets having the same number of elements and the remainingsets having a number of elements different from that of said first threesets.
 16. The apparatus as recited in claim 14 wherein the setsrepresenting the elements in said first ring corRespond to quadrantswhich are asymmetrical due to the use of said toggle flip-flops in saidcounters, whereby the total number of transistors in said counters areminimized.
 17. The apparatus as recited in claim 14 wherein said timeindicating elements are light emitting diodes.
 18. The apparatus asrecited in claim 14 wherein said means for generating a series of pulsedelectrical signals includes a crystal oscillator having a frequencywhich is some power of 2 and a series of cascaded flip-flops coupled tothe output of said oscillator for counting down the output of saidoscillator to 1 Hz, intermediate outputs of said cascaded series offlip-flops being used in the generation of said sampling pulses.
 19. Theapparatus as recited in claim 18 wherein the output of one of saidcascaded flip-flops in said means for generating a series of pulsedelectrical signals is applied to the input of the first of said threecounters to alter the time indicated by said display.